First, a semiconductor device related to the present invention is explained hereinafter with reference to FIG. 8. FIG. 8 schematically illustrates a semiconductor structure of a vertical type GaN field effect transistor (hereinafter called vertical type GaN FET). Note that a vertical type GaN FET shown in FIG. 8 is disclosed in Non patent literature 1, for example.
In the vertical type GaN FET shown in FIG. 8, an n-type GaN layer (102) is formed on a high concentration n-type GaN layer (101). A p-type GaN layer (103) is formed thereon. An n-type GaN layer (104) is formed thereon. A source electrode (111) in ohmic contact is formed thereon. Further, a drain electrode (113) in ohmic contact is formed on the high concentration n-type GaN layer (101) which is exposed by removing a semiconductor layer. Furthermore, a gate electrode (112) is formed on the exposed side of the n-type GaN layer (104) and the p-type GaN layer (103) through a gate insulation film (121).
This vertical type GaN FET shown in FIG. 8 changes an electron concentration accumulated on the interface between the p-type GaN layer (103) and the gate insulation film (121) with a voltage applied to the gate electrode (112). By doing so, a current flowing between the source electrode (111) and the drain electrode (113) is controlled and the vertical type FET is operated.
FIG. 9 is a band energy distribution chart of the vertical type GaN FET shown in FIG. 8. The line between A and B shown in FIG. 9 corresponds to the line between A and B shown in FIG. 8. Further, Vds in FIG. 9 represents a drain voltage. Lch represents the thickness of the p-type GaN layer (103) and Na represents the impurity concentration thereof. Further, Ldr represents the thickness of the n-type GaN layer (102) and Nd represents the impurity concentration thereof. Further, xp and xn respectively represent the spread of the depletion layer (depletion layer width) from the pn junction surface of these semiconductor layers. The electrical charge in the depletion layer of the p-type GaN layer (103) and that of the n-type GaN layer (102) are equal. Therefore, the following expression holds.xp×Na=xn×Nd  Expression (1)
The withstanding voltage VB of the vertical type GaN FET shown in FIG. 8 is designed with the thickness of the n-type GaN layer (102). Namely, when Ecrit represents the breakdown field of GaN, the following expression holds under the conditions in which the n-type GaN layer (102) is completely depleted.VB=Ecrit×Ldr  Expression (2)
Further, the on-resistance RON of the vertical type GaN FET in FIG. 8 can be approximately expressed in the following expression.RON∝1/(Lch+Ldr)  Expression (3)
FIG. 10 shows the relationship between the withstanding voltage VB and the on-resistance RON calculated by the above relational expression of the expression (2) and (3). The horizontal axis in FIG. 10 represents the withstanding voltage VB (V) and the vertical axis represents the on-resistance RON (mΩcm2). As shown in FIG. 10, in the region where the withstanding voltage VB=103 (V) or higher, the withstanding voltage VB and the on-resistance RON decrease at the same time as Ldr decreases. Therefore, the relationship approaches to a GaN theoretical limit. In the region where the withstanding voltage VB=103 or lower, the withstanding voltage VB decreases, whereas Lch stays constant as Ldr decreases. Therefore, the resistance of the p-type GaN layer (103) becomes dominant, and the on-resistance RON has a constant value. In order to reduce the on-resistance RON in the region where the withstanding voltage VB=103 (V) or lower, the reduction in Lch is effective. However, when the depletion layer in the p-type GaN layer (103) reaches the whole region of the p-type GaN layer (103), a space charge limited current flows because of a punch-through phenomenon and the off-operation cannot be maintained. Namely, in order to maintain the normal switching operation, the relation Lch>xp needs to be satisfied. The lower limit of Lch is determined by the following expression in combination with the expression (1).Lch>xn×Nd/Na  Expression (4)
When the on-resistance RON of the device is reduced in the semiconductor structure shown in FIG. 8, a punch through phenomenon may occur in the region where the withstanding voltage VB=103 or lower. Therefore, there is a limitation in reducing the on-resistance by thinning the p-type GaN layer (103).
Particularly, it is difficult for the p-type GaN layer (103) to have high concentration (about 1017 cm−3). Therefore, the depletion layer width xp of the p-type GaN layer (103) becomes large, and there is a limitation in reducing the on-resistance by thinning the p-type GaN layer (103).
For this reason, the development of a semiconductor device which is capable of suppressing the occurrence of a punch-threw-phenomenon is required.
As a related art document filed prior to the present invention, there is a literature which discloses a technique that enables a small chip size and a high withstanding voltage operation in a field effect transistor using a nitride compound semiconductor (for example, refer to Patent literature 1).
Further, there is a literature which discloses a technique that realizes a buffer layer with a lower resistance in an electric device (element for power electronics) in which a current passes through a SiC substrate and each nitride compound semiconductor layer to operate the electric device (for example, refer to Patent literature 2).
Further, there is a literature which discloses a nitride compound semiconductor that has a lower resistance circuit element and a high operation voltage (for example, refer to Patent literature 3).
Further, there is a literature which discloses a semiconductor circuit element with a lower electric resistance, which includes a mesa part where a polarization caused by the lamination of semiconductor layers is reduced and carriers can smoothly move (for example, refer to Patent literature 4).
[Patent Literature 1]    Japanese Unexamined Patent Application Publication No. 2007-142243
[Patent Literature 2]    Japanese Unexamined Patent Application Publication No. 2007-134517
[Patent Literature 3]    Japanese Unexamined Patent Application Publication No. 2007-59719
[Patent Literature 4]    Japanese Unexamined Patent Application Publication No. 2006-324279
[Non Patent Literature 1]
H. Otake et al. Japanese Journal of Applied Physics, Vol. 46, No. 25, 2007, pp. L599-L601